1. Field of the Invention
The present invention relates to a predrive circuit which drives output elements such as power MOS (Metal-Oxide Semiconductor) FET and IGBT (Insulated Gate Bipolar Transistor), and a display device using the predrive circuit.
2. Description of the Related Art
Conventionally, “A New Driving Technology for PDPs with Cost Effective Sustain Circuit” has been disclosed in the “SID 01 DIGEST”, page 1236–1239, as a method of reducing circuit cost of plasma display device, which is one of the flat panel display devices. As a similar reference, Japanese Patent Application Laid-open No. 2002-062844 (Patent No. 3201603) has disclosed substantially the same contents.
Furthermore, for example, one of the plasma display devices, AC-Plasma Display Panel (AC-PDP) is classified into a 2-electrode type which carries out selection (address) discharge and sustaining discharge by two electrode, and a 3-electrode type which carries out address discharge using a third electrode. Generally, there have been two structure types for the above 3-electrode type. The one type has the third electrode being formed on a same side of the substrate that includes a first electrode and a second electrode which carries out sustaining discharge. Another type has the third electrode being formed on the other side of the substrate.
Since both the PDP devices described above are based on a same principle of operation, the structure of the 3-electrode type with the first electrode and the second electrode being formed on a first substrate and with the third electrode being formed on a second substrate will be explained below.
FIG. 22 is a diagram showing an overall structure of an AC-PDP device. The AC-PDP device 1 in FIG. 22 comprises plural cells, each cell representing one pixel of a displayed image and being arranged in a matrix form. The respective cells are arranged in a matrix with m rows and n columns, as can be seen by cells Cmn in the drawing. Additionally, in the AC-PDP device 1, scan electrode Y1 to Yn and common electrodes X are installed in parallel to each other on the first substrate, and address electrodes A1 to Am are installed orthogonally to these electrodes Y1 to Yn and electrodes X on the second substrate oppose the first substrate. The common electrodes X are arranged adjacent to the respective scanning electrodes Y1 to Yn, and one ends of which are connected to each other.
A common terminal of the common electrodes X is connected to an output terminal of an X-side circuit 2, and the scanning electrodes Y1 to Yn are respectively connected to output terminals of a Y-side circuit 3. The address electrodes A1 to Am are connected to output terminals of an address-side circuit 4. The X-side circuit 2 comprises a circuit that conducts discharge continuously. The Y-side circuit 3 comprises a circuit that conducts line-sequential scanning and a circuit that discharges continuously. The address-side circuit 4 comprises a circuit that selects which column to display.
These X-side circuit 2, Y-side circuit 3, and address-side circuit 4 are controlled by control signals supplied from a drive control circuit 5. Namely, the address-side circuit 4 and the circuit which conducts line-sequential scanning in the Y-side circuit determine which cell to be lighted. Then the X-side circuit 2 and the Y-side circuit 3 conduct discharge continuously to carry out a display operation of the PDP device.
The drive control circuit 5 generates the control signals based on a display data D, a clock CLK which indicates a timing to read the display data D, a horizontal synchronization signal HS, and a vertical synchronization signal VS, all being supplied externally. Then these control signals will be supplied to the X-side circuit 2, the Y-side circuit 3, and the address-side circuit 4.
FIG. 23A is a diagram showing a cross sectional structure of a cell at row i and column j as one pixel. In FIG. 23A, a common electrode X and a scan electrode Yi are formed on a front glass substrate 11. Over them, a dielectric layer 12 is deposited as insulation against a discharge space 17. Further, an MgO (magnesium oxide) protective film 13 is deposited over the dielectric layer 12.
On the other hand, an address electrode Aj is formed on a rear glass substrate 14 which is placed oppose the front glass substrate 11. Over the electrode Aj, there is deposited a dielectric layer 15. Further, a phosphor 18 is deposited over the dielectric layer 15. Ne+Xe penning gas or the like is enclosed between the MgO protective film 13 and the dielectric layer 15.
FIG. 23B is a diagram for describing a capacity Cp of the AC-PDP device. As shown in FIG. 23B, there are capacitive components Ca, Cb, and Cc in the discharge space 17, between the common electrode X and the scan electrode Yi, and on the front glass substrate 11, respectively. By adding these capacitive components, a capacity Cpcell of a cell will be defined (Cpcell=Ca+Cb+Cc). A sum of the capacity Cpcell of every cell defines a panel capacity Cp.
FIG. 23C is a diagram for describing an emission of fluorescence of the AC-PDP device. As shown in FIG. 23C, red, blue, and green phosphors 18 are arranged in a stripe pattern and painted between ribs 16. The phosphor 18 emits fluorescence when it is excited by discharge between the common electrode X and the scan electrode Y.
As one method of driving such AC-PDP device, use of a driving system shown in FIG. 24 is suggested. This device conducts discharge between electrodes utilizing a potential difference produced by applying a positive voltage to one electrode and a negative voltage to the other electrode.
FIG. 24 is a diagram showing a circuitry example of the driving system of the AC-PDP device.
In FIG. 24, a capacitive load 20 (hereinafter, referred to as a “load 20”) is a sum of capacity of every cell being formed between one common electrode X and one scan electrode Y. The common electrode X and the scan electrode Y are formed on the load 20. Here, scan electrode Y is any electrode of the scan electrodes Y1 to Yn.
First, on the common electrode X side, switches SW1 and SW2 are connected serially between a power supply line of voltage (Vs/2) supplied from a power supply not shown in the diagram and ground (GND). A point of interface between the two switches SW1 and SW2 is connected to one terminal of a capacitor C1, and a switch SW3 is connected between the other terminal of the capacitor C1 and the GND.
Switches SW4 and SW5 are connected serially to the both terminal of the capacitor C1. Then a point of interface between these switches SW4 and SW5 is connected to the common electrode X of the load 20 through an output line OUTC from its middle and further connected to a power recovery circuit 21. A switch SW6 with a resistor R1 is connected between a second signal line OUTB and a power supply line which generates a write voltage Vw.
The power recovery circuit 21 comprises two coils L1 and L2 which are both connected to the load 20, a diode D2 and a transistor Tr1 which are both connected serially to one coil L1, and a diode D3 and a transistor Tr2 which are both connected serially to the other coil L2. Furthermore, the power recovery circuit 21 comprises a capacitor C2 which is connected between a point of interface of the two transistors Tr1 and Tr2, and the second signal line OUTB.
Then there are configured two systems of serial resonance circuits by the capacitive load 20 and the coils L1 and L2 which are both connected to this load 20. In other words, this power recovery circuit 21 has two systems of L-C resonance circuit supplying an electric charge to the panel by resonance between the coil L1 and the load 20, and recovering the electric charge by resonance between the coil L2 and the load 20.
On the other hand, on the scan electrode Y side, switches SW1′ and SW2′ are connected serially between a power supply line of voltage (Vs/2) supplied from a power supply not shown in the diagram and the GND. A point of interface between these two switches SW1′ and SW2′ is connected to one terminal of a capacitor C4, and a switch SW3′ is connected between the other terminal of this capacitor C4 and the GND.
A switch SW4′ which is connected to the one terminal of the capacitor C4 is connected to a cathode of a diode D7. An anode of the diode D7 is connected to the other terminal of the capacitor C4. A switch SW5′ which is connected to the other terminal of the capacitor C4 is connected to an anode of a diode D6. A cathode of the diode D6 is connected to the one terminal of the capacitor C4.
Then, one end of the switch SW4′ which is connected to the cathode of the diode D7 and one end of the switch SW5′ which is connected to the anode of the diode D6 are both connected to the load 20 through a scan driver 22, and further connected to a power recovery circuit 21′. A switch SW6′ with a resistor R1′ is connected between a fourth signal line OUTB′ and a power supply line which generates a write voltage Vw.
The power recovery circuit 21′ comprises two coils L3 and L4 which are both connected from the load 20 through the scan driver 22, a diode D4 and a transistor Tr3 which are both connected serially to one coil L3, and a diode D5 and a transistor Tr4 which are both connected serially to the other coil L4. Furthermore, the power recovery circuit 21′ comprises a capacitor C3 which is connected between a common terminal of the transistors Tr3 and Tr4, and the fourth signal line OUTB′.
This power recovery circuit 21′ also has two systems of L-C resonance circuit, supplying an electric charge by resonance between the coil L4 and the load 20, and recovering this electric charge by resonance between the coil L3 and the load 20.
In addition to the above configuration, the scan electrode Y side also comprises three transistors Tr5, Tr6, and Tr7, and two diodes D6 and D7. When the transistor Tr5 is turned on, an effect of a resistor R2 connected to this transistor slacks a waveform of a pulse voltage which is applied to the scan electrode Y. The transistor Tr5 and resistor R2 are connected in parallel to the switch SW5′.
The transistors Tr6 and Tr7 also have a purpose of applying a potential difference of (Vs/2) to both ends of the scan driver 22 during an address period which will be described later. When the switch SW2′ and the transistor Tr6 are both turned on, a voltage of a topside of the scan driver 22 becomes ground level. When the transistor Tr7 is turned on, a negative voltage (−Vs/2) which is output to the fourth signal line OUTB′ according to an electric charge stored in the capacitor C4 will be applied to a downside of the scan driver 22. That enables the scan driver 22 to apply the negative voltage (−Vs/2) to the scan electrode Y when a scan pulse is output.
The above-mentioned switches SW1 to SW6, SW1′ to SW6′ and transistors Tr1 to Tr7 are controlled by control signals respectively supplied from a drive control circuit 31. The drive control circuit 31 is configured using a logic circuit, etc., and it generates the control signals based on a display data D, a clock CLK, a horizontal synchronization signal HS, and a vertical synchronization signal VS, all being supplied externally. Then these control signals will be supplied to the switches SW1 to SW6, SW1′ to SW6′, and the transistors Tr1 to Tr7.
FIG. 24 only shows control lines from the drive control circuit 31 which are connected to the switches SW4, SW5, SW4′, SW5′, and transistors Tr1 to Tr4. However, the other switches SW1 to SW6, SW1′ to SW6′, and transistors Tr1 to Tr7 are also connected to the drive control circuit 31 by control lines.
FIG. 25 is a time chart showing drive waveforms of the driving system of the AC-PDP device as configured in FIG. 24 and it shows one sub-field among plural sub-fields which compose one frame. One sub-field is divided into a reset period which includes a total write period and a total erase period, an address period, and a sustain discharge period.
In FIG. 25, during the reset period, the switches SW2 and SW5 are turned on, while the switches SW1, SW3, SW4, and SW6 are turned off on the common electrode X side. Accordingly, a voltage of the signal line OUTB decreases to the voltage (−Vs/2) according to an electric charge stored in the capacitor C1. Then the voltage (−Vs/2) is output to the output line OUTC through the switch SW5 and applied to the common electrode X.
On the other hand, on the scan electrode Y side, the switches SW1′, SW4′, and SW6′ are turned on, while the switches SW2′, SW3′, and SW5′ are turned off. Then a sum of the voltage Vw and a voltage (Vs/2) stored in the capacitor C4 is applied to the output line OUTC′. Accordingly, this voltage (Vs/2+Vw) is applied to the scan electrode Y of the load 20. At this time, by an effect of the resistor R1′ in the switch SW6′, the voltage gradually increases over time.
As a result, a potential difference between the common electrode X and the scan electrode Y becomes (Vs+Vw), causing discharge on all cells of all display lines regardless of a prior display status, and there are formed wall charges (total write).
Next, the voltage of the common electrode X and the scan electrode Y are returned to the ground level by controlling each switches appropriately, to reverse the status of the common electrode Y side and the scan electrode X side. Namely, on the common electrode X side, the switches SW1, SW4, and SW6 are turned on while the switches SW2, SW3, and SW5 are turned off, and on the scan electrode Y side, the switches SW2′ and SW5′ are turned on while the switches SW1′, SW3′, SW4′, and SW6′ are turned off.
Then the applied voltage of the common electrode X increases gradually over time from the ground level to the voltage (VS/2+Vw), while the applied voltage of the scan electrode Y decreases to the voltage (−Vs/2). Accordingly, the voltages of their wall charges of all cells reach and exceed the firing potential to thereby start discharge. At this time, by gradually increasing the applied voltage to the common electrode X over time as mentioned above, weak discharge is conducted so as to erase the wall charges except some part (total erase).
Next, during the address period, line-sequential address discharge is conducted in order to turn on and/or off each cell according to the display data. At this time, on the common electrode X side, the switches SW1, SW3, and SW4 are turned on, and the switches SW2, SW5, and SW6 are turned off, thereby increasing a voltage of a first signal line OUTA to a voltage (Vs/2) which is supplied through the switch SW1. This voltage (Vs/2) is output to the output line OUTC through the switch SW4 and applied to the common electrode X on the load 20.
When applying a voltage to a scan electrode Y which corresponds to one display line, the switch SW2′ and the transistor Tr6 are turned on, so that the voltage of the topside of the scan driver 22 becomes ground level. Then the transistor Tr7 is turned on to apply the negative voltage (−Vs/2), which is output to the fourth signal line OUTB′ according to the electric charge stored in the capacitor C4, will be applied to the downside of the scan driver 22. Consequently, the negative voltage (−Vs/2) is applied to the scan electrodes Y on the load 20 which are line-sequentially selected, and the ground level voltage is applied to the scan electrodes Y on the load 20 which are not line-sequentially selected.
At this time, address pulses of voltage Va are selectively applied to address electrodes Aj between address electrodes A1 to Am, corresponding to cells which conduct sustaining discharge, i.e., cells to be lighted. Then discharges occur between the address electrodes Aj of the cells to be lighted and the line-sequentially selected scan electrodes Y. Using these discharges as priming, other discharges occur immediately between the common electrodes X and the scan electrodes Y. As a result, wall discharges needed for next sustaining discharges are stored in the MgO protective film above the common electrodes X and the scan electrodes Y of the selected cells.
Next, during the sustain discharge period, on the common electrode X side, the switches SW1 and SW3 are turned on first, while the other switches SW2 and SW4 to SW6 are turned off. The voltage of the first signal line OUTA becomes (+Vs/2), and the voltage of the second signal line OUTB becomes ground level. The transistor Tr1 in the power recovery circuit 21 is turned on to conduct L-C resonance between the coil L1 and the load 20, and then the electric charge stored in the capacitor C2 is supplied to the load 20 through the transistor Tr1, the diode D2, and the coil L1.
An electric current which is supplied from the capacitor C2 to the common electrode X through the switch SW3 on the common electrode X side is further supplied to the GND of the scan electrode Y side through a diode in the scan driver 22, the diode D6, a third signal line OUTA′, and the switch SW2′ by turning on the switch SW2′. This electric current flow causes the voltage of the common electrode X to increase gradually as shown in FIG. 25. At around a peak voltage which occurs during this resonance, the SW4 is turned on to clamp the voltage of the common electrode X on the voltage (Vs/2).
On the scan electrode Y side, the transistor Tr3 in the power recovery circuit 21′ is turned on. Then L-C resonance occurs between the coil L3 and the load 20, so that an electric current, which is supplied from the switch SW3 and the capacitor C1 to the electrode X through the first signal line OUTA and the switch SW4 on the common electrode X side, is supplied to the GND of the scan electrode Y side through the diode in the scan driver 22, the diode D4 in the power recovery circuit 21′, and further through the transistor Tr3, the capacitor C3, the capacitor C4, and the switch SW2′. This electric current flow causes the voltage of the scan electrode Y to decrease gradually as shown in FIG. 25. At this time, a part of the electric charge is recovered in the capacitor C3. At around a peak voltage which occurs during this resonance, the switch SW5′ is turned on to clamp the voltage of the scan electrode Y on the voltage (−Vs/2).
Similarly, when the applied voltage (−Vs/2) of the common electrode X and the scan electrode Y are increased to the ground level (0(zero) V), the applied voltage is increased gradually by supplying the electric charges recovered in the capacitor C2 and C3 in the power recovery circuit 21 and 21′.
On the other hand, when the applied voltage (Vs/2) of the common electrode X and the scan electrode Y are decreased to the ground level (0(zero) V), the applied voltage is decreased gradually by supplying the electric charge stored in the load 20 to the GND, and a part of the electric charge is recovered to each capacitor C2, C3 in the power recovery circuit 21 and 21′.
As described above, during the sustain discharge period, the sustaining discharge is conducted by alternatively applying the voltages with different polarity (+Vs/2, −Vs/2) to the common electrode X and the scan electrode Y of each display line, in order to display one sub-field of a picture.
Additionally, in the driving circuit of the AC-PDP device, the drive control circuit 31 which is configured by logic circuits, etc., has a reference potential of the GND level. This drive control circuit 31 supplies control signals to output elements, in other words, the switches SW4, SW5, SW4′ SW5′, and transistors Tr1 to Tr4 in the power recovery circuit 21 and 21′, so that they apply the voltages to the common electrode X and the scan electrode Y. However, reference potentials for these output elements will change according to the driving operation. Accordingly, there has been a problem such as, for example, when the drive control circuit 31 generates the control signals and supplies them to the output elements, there is a possibility of a back flow of a voltage variation from the output elements to the drive control circuit 31, thereby impressing a high voltage.
As a solution to solve this problem, conversion of the reference potentials by level shifting the control signals output from the control circuit using a level shift circuit is conceivable. For example, a method of using a predrive circuit between the drive control circuit 31 and the output elements will be explained. This predrive circuit outputs control signals with converted reference potentials to the output elements which apply voltage. In particular, this predrive circuit level shifts the reference potentials of the control signals according to the reference potentials of the output elements (−Vs/2 to Vs/2), thereby outputting these level-shifted control signals to the output elements.
FIG. 26 is a diagram showing an example of the predrive circuit which corresponds to a variation of the reference potential of the output elements side. This predrive circuit P1 shown in FIG. 26 is an integrated circuit (semiconductor circuit) which will be inserted between the drive control circuit 31 and the switch SW4 as an output element shown in FIG. 24. In FIG. 26, an amplification/level shift circuit P10 level shifts and amplifies a reference potential (GND) of a control signal CLT1 which is output from the drive control circuit 31 to the reference potential of the output elements side (−Vs/2 to Vs/2). The output circuit P11 drives the switch SW4 according to the signal output from the amplification/level shift circuit P10.
An input terminal of the amplification/level shift circuit P10 is connected to an input terminal VIN of the predrive circuit P1, in which the control signal CTL1 is input. A p-type substrate P13 is a semiconductor substrate to which a p-type impurity is added. The substrate P13 is connected to a reference potential terminal K1 of the predrive circuit P1, in which the reference potential (GND) of the control signal CTL1 is input.
The output circuit P11 is also configured by n-channel MOSFETs Tr11 and Tr12, and an inverter circuit INV13 as shown in FIG. 26. The Tr11 is a transistor which is turned on and/or off by control signals output from the amplification/level shift circuit P10, which controls whether or not to output a voltage Vcc supplied from a power supply terminal V1 to the output terminal Vo. The Tr12 is a transistor which is turned on and/or off by the control signals supplied from the amplification/level shift circuit P10 and inverted by the INV13, which controls whether or not to output a reference potential (−Vs/2 to Vs/2) supplied from a reference potential terminal K2.
A parasitic diode 12 visually represents a parasitic diode which is generated at a pn junction point formed by a part of the substrate P13 and a part of the Tr12. Through the parasitic diode 12, the substrate P13 is connected to the reference potential terminal K2 to which the reference potential (−Vs/2) of the control signal output from the predrive circuit P1 is applied. An anode terminal of the parasitic diode is connected to the substrate P13.
However, in the driving circuit of the AC-PDP device, the drive control circuit 31 which is configured by logic circuits, etc., has a reference potential of the GND level. This drive control circuit 31 supplies control signals to output elements, in other words, the switches SW4, SW5, SW4′ SW5′, and the transistors Tr1 to Tr4 in the power recovery circuit 21 and 21′, so that they apply the voltages to the common electrode X and the scan electrode Y. However, reference potentials for these output elements will change according to the driving operation. Accordingly, for example, when the drive control circuit 31 generates the control signals and supplies them to the output elements, there is a possibility of a back flow of a voltage variation from the output elements to the drive control circuit 31, thereby impressing a high voltage.
As a solution to solve this problem, conversion of the reference potentials by level shifting the control signals output from the control circuit using a level shift circuit is conceivable. However, there has been a problem of using generally available level shift circuits. By using these circuits, there is a possibility that the control signals would not be transmitted adequately when the reference potentials generated on the output elements side turn to high voltage.
In addition, as described above, when supplying the control signals generated by the drive control circuit 31 to the output elements, there is a possibility that a high voltage is impressed to the drive control circuit 31 due to the voltage variation of the output elements, so that the control signals would not be stably transmitted to the output elements.
To prevent the high voltage impression to the drive control circuit 31, the above described predrive circuit P1 can generate control signals, based on the control signals having reference potential of 0(zeoro) V, in order to drive the switch SW4 whose reference potential changes from −Vs/2 to Vs/2. However, there has been a problem when the GND is applied to the reference potential terminal K1, and the negative voltage −Vs/2 is applied to the reference potential terminal K2, it is possible that an abnormal current Ip, due to the parasitic diode 12, occurs and disturbs the normal operation of the predrive circuit P1.
The present invention has been made considering the problems described above, and its object is to provide a predrive circuit, a drive circuit, and a display device which are capable of driving the output elements so as to transmit the control signals stably even when the reference potentials generated on the output elements side turn to high voltage.
The present invention has been made considering the problems described above, and its object is to provide a predrive circuit and a display device which are capable of driving the output elements so as to transmit the control signals stably even when the reference potentials generated on the output elements side turn to high voltage.
Another object of the present invention is to provide a predrive circuit and a display device both of which are suitable for an integrated circuit which is capable to operate normally even when the reference potentials generated on the output elements side turn to negative voltages.